The inventive concepts relate to integrated circuit devices and/or methods of fabricating the same, and more particularly, to integrated circuit devices including a contact plug connected to an active region of a substrate, and/or methods of fabricating the same.
Along with ultra-high integration of integrated circuit devices and reduction in lengths of gates of field effect transistors (FETs), in order to overcome limits of element characteristics of planar metal oxide semiconductor FETs (MOSFETs), efforts to develop an element including a FinFET having a 3-dimensional structured channel are being made. Further, along with reduction in feature sizes of FinFETs, a contact resistance between a source/drain region and a contact plug connected to the source/drain region acts as a main factor of parasitic resistances of integrated circuit devices. Therefore, there is a need to reduce or minimize a contact resistance between a source/drain region and a contact plugs of a FinFET.